Power saving method for performing additions and subtractions and device thereof and especially a power saving address generation unit and a method thereof.
Multi-bit adders, and especially high-speed adders are comprised of many transistors. For example, a 32 bit adder is comprised of more than a thousand CMOS transistors. 32-bit adders and even larger adders are extensively used in modern processor address generating units.
A premium is placed upon low power consumption of modern processors, especially in electrical devices that are powered by batteries. It is very important to reduce the energy consumption associated with very frequent operations such as subtraction and additions. It is convenient to reduce the power associated with address generation, especially when the subtraction and addition involve an operand (xe2x80x9coldxe2x80x9d address) and a constant K, wherein K usually equals 2n.
There is a need of a power saving method for performing additions and subtractions and device thereof and especially a power saving address generation unit and a method thereof.